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1 of 14 19 - 6687 ; rev 5/13 general description the ds1775 digital thermometer and thermostat provides temperature readings that indicate the devices temperature. thermostat settings and temperature readings are all communicated to/from the ds1775 over a simple 2 - wire se rial interface. no additional components are required; the device is truly a temperature - to - digital converter. for applications that require greater temperature resolution, the user can adjust the readout resolution from 9 to 12 bits. this is particularl y useful in applications where thermal runaway conditions must be detected quickly. the open - drain thermal alarm output, o.s., becomes active when the temperature of the device exceeds a user - defined temperature t os . the number of consecutive faults requir ed to set o.s. active is configurable by the user. the device can also be configured in the interrupt or comparator mode, to customize the method which clears the fault condition. as a digital thermometer, the ds1775 is software compatible with the ds75 2 - wire thermal watchdog. the ds1775 is assembled in a compact 5 - pin sot23 package, allowing for low- cost thermal monitoring/control in space - constrained applications. the low thermal mass allows for time constants previously only possible with thermistors. a pplications ? personal computers/servers/workstations ? cell phones ? office equipment ? any thermally - sensitive system features ? temperature measurements require no external components ? measures t emperatures from -55 c to +125 c (-67 f to +257 f) ? 2.0 c thermometer accuracy ? thermometer resolution is conf igurable from 9 bits to 12 b its (0.5 c to 0.0625 c resolution) ? user - definable thermostat settings ? data i s read from/written to through a 2-w ire serial interfa ce ? 2.7v to 5.5v wide power -supply ran ge ? software compatible with ds75 2- wire thermal watchdog in thermometer m ode ? space -conscious 5-pin sot23 p ackage with low thermal time con stant pin configuration pin description gnd ground scl 2- wire serial clock sda 2- wire serial data input/output v dd power -supply voltage o.s. thermostat output signal ordering information appears at end of data sheet . ds1775 digital thermometer and thermostat in sot23 sot23 3 2 1 5 4 sda v dd scl gnd o.s. downloaded from: http:///
ds1775 2 of 14 table 1. detailed pin description pin name function 1 scl clock input/output for 2- wire serial communication port . this input should be tied to gnd for stand-alone thermostat operation. 2 gnd ground 3 o.s. thermostat output. open -drain output becomes active when temperature exceeds t os . device configurat ion defines m eans to clear overtemperature state. 4 v dd supply voltage 2.7v to 5.5v input power pin 5 sda data input/output for 2- wire serial communication po rt. in the stand- alone thermostat mode, this input selects hysteresis. detailed description figure 1 shows a block diagram of the ds1775. the ds1775 consists of five major components: 1. precision temperature sensor 2. analog- to - digital converter 3. 2- wire interface electronics 4. data registers 5. thermostat comparator the factory - calibrated temperature sensor requires no e xternal components. upon power - up, the ds1775 begins temperature conversions with the default resolution of 9 bits (0.5 c resolution). the host can periodically read the value in the temperature register, which contains the last completed conversion. as co nversions are performed in the background, reading the temperature re gister does not affect the conversion in progress. in power - sensitive applications , the user can put the ds1775 into a shutdown mode, under which the sensor complete and store the conversion in progress and revert to a low - power standby state. in applications where small incremental temperature changes are critical, the user can change the conversion resolution from 9 bits to 10, 11, or 12. each additional bit of resolution approxim ately doubles the conversion time. this is accomplished by programming the configuration register. the configuration register defines the conversion state, thermometer resolution/conv ersion time, active state of the thermostat output, number of consecutive faults to trigger an alarm condit ion, and the method to terminate an alarm condition. the user can also program overtemperature (t os ) and under temperature (t hyst ) setpoints for thermostatic operation. the power - up state of t os is +80 c and that for t hyst is +75 c. the result of each temperature conversion is compared with the t os and t hyst setpoints. the ds1775 offers two modes for temperature control, the comparator mode and the interrupt mode. this a llows the user the flexibility to customize the condition th at would generate and clear a fault condition. regardless of the mo de chosen, the o.s. output become s active only after the measured temperature exceeds the respective trip - point a consecutive number of times; the number of consecutive conversions beyond t he limit to generate an o.s. is programmable. the power - up state of the ds1775 is in the comparator mode with a single fault generating an active o.s. digital data is written to/read from the ds1775 via a 2 - wire interface, and all communication is msb fir st. downloaded from: http:///
ds1775 3 of 14 figure 1. block diagram operation measuring temperature the core of ds1775 functionality is its direct - to - digital temperature sensor. the ds1775 measures temperature through the use of an on - chip temperature measurement technique with an operatin g range from -55 c to +125 c. temperature conversions are initiated upon power - up, and the most recent result is stored in the thermometer register. conversions are performe d continuously unless the user intervenes by altering the configuration register to put the ds1775 into a shutdown mode. regardless of the mode used, the digital temperature can be retrieved from the tempera ture register by setting the pointer to that location (00h, power - up default). the ds1775 power - up default has the sensor automatically performing 9- bit conversions continuously. details on how to change the settings aft er power - up are contained in the programming section. the resolution of the temperature conversion is configurable (9, 10, 11, or 12 bits), with 9- bit readings the def ault state. this equates to a temperature resolution of 0.5 c, 0.25 c, 0.125 c, or 0.0625 c. following each conversion, thermal data is stored in the thermometer regis ter in twos complement format; the information can be retrieved over the 2 - wire interfac e with the device pointer set to the temperature register. table 2 describes the exact relationship of output d ata to measured temperature. the table assumes the ds1775 is configured for 12 - bit resolution; if the device is configured in a lower resolution mode, those bits contain zeros. the data is transmitted serially ov er the 2 - wire serial interface, msb first. the msb of the tem perature register contains the sign (s) bit, denoting whether the temperature is positive or negative. for fahrenheit usage, a lookup table or conversion routine must be use d. downloaded from: http:///
ds1775 4 of 14 table 2. temperature/data relationships s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb msb (unit = c) lsb 2 -1 2 -2 2 -3 2 -4 0 0 0 0 lsb temp erature ( c) digital output ( binary ) digital output ( hex ) +125 0111 1101 0000 0000 7d00h +25.0625 0000 1010 0010 0000 1910h +10.125 0000 1010 0010 0000 0a20h +0.5 0000 0000 1000 0000 0080h 0 0000 0000 0000 0000 0000h -0.5 1111 1111 1000 0000 ff80h -10.125 1111 0101 1110 0000 f5e0h -25.0625 1110 0110 1111 0000 e6f0h -55 1100 1001 0000 0000 c900h thermostat control in its comparator operating mode, the ds1775 functions as a thermostat with progra mmable hysteresis, as shown in figure 2. when the ds1775s temperature meets or exceeds the value stored in the high temperature tr ip register (t os ) a consecutive number of times, as defined by the configuration register , the output becomes active and stays active until the first time that the te mperature falls below the temperature stored in the low temperature trigger register (t hys t ). in this way, any amount of hysteresis may be obtained. the ds1775 powers up in the comparator mode with t os = +80 c and t hyst = +75 c and can be used as a stand -alone thermostat (no 2-wire interface required) with those setpoints. in the interrupt mode, the o.s. output first become s active following the programmed number of consecutive conversions above t os . the fault can only be cleared by either setting the ds1775 in a shutdown mode or by reading any register (temperature, configura tion, t os , or t hys t ) on the device. following a clear, a subsequent fault can only occur if consecutive conversions fall below t hyst . this interrupt/clear process is thus cyclical (t os , clear, t hyst , clear, t os , clear, t hyst , clear, etc. ). only the first of multiple consecutive t os violations activate s o.s., even if each fault is separated by a clearing function. the same situation applies to multiple consecutive t hyst events. downloaded from: http:///
ds1775 5 of 14 figure 2. o.s. output transfer function regardless of the mode chosen, the o.s. output is ope n- drain and the active state is set in the configuration register. the power - up default is active low. see the programming section for instructions in adjusting the thermostat setpoints, thermostat mode, and o.s. active state. programming there are three areas of interest in programming the ds1775: the configuration regis ter, the t os register, and the t hyst register. all programming is done via the 2 - wire interface by setting the pointer to the appropriate location. table 3 illustrates the pointer settings for the four registers of the ds1775. table 3. pointer register structure pointer active register 00h temperature (default) 01h configuration 02h t hyst 03h t os the ds1775 powers up with the temperature register selected. if the host wishes to cha nge the data pointer, it simply addresses the ds1775 in the write mode (r/ w = 0), receives an acknowledge, and writes the 8 bits that correspond to the new desired location. the las t pointer location is always maintained so that consecutive reads from the same register do not require the host to always provide a pointer address. the only exception is at power - up, in which case the pointer is always set to 00h, the downloaded from: http:///
ds1775 6 of 14 temperature register. the pointer address must always pr e ced e data in wr iting to a register, regardless of which address is currently selected. see the 2- wire serial data bus section for details of the 2 - wire bus protocol. configuration register programming the configuration register is accessed if the ds1775 pointer is c urrently set to the 01h location. writing to or reading from the register is determined by the r/ w bit of the 2 - wire control byte ( s ee the 2-w ire serial data bus section). data is read from or written to the configuration regis ter msb first. the format of the register is illustrated in table 4 . the effect each bit has on ds1775 functionality is described below along with the power - up state of the bit. the user has read/write access to all bit s in the configuration register. the entire register is volatile, and thus it power s up in the default state. table 4 . configuration/status register 0 r1 r0 f1 f0 pol tm sd msb lsb sd = shutdown bit. if sd is 0, the ds1775 continuously perform s temperature conversions and store s the last completed result in the th ermometer register. if sd is changed to 1, the conversion in progre ss is completed and stored; then the device revert s to a low - power standby mode. the o.s. output is cleared if the device is in the interrupt mode and remain s unchanged in the comparator mo de. the 2 - wire port remains active. the power -up default state is 0 (continuous conversion mode). tm = thermostat mode. if tm = 0, the ds1775 is in the comparator mode. tm = 1 sets the device to the interrupt mode. see the thermostat control section for a description of the difference between the two modes. the power-up default state of the tm bit is 0 (comparator mode). pol = o.s. polarity bit. if pol = 1, the active state of the o.s. output is high. a 0 stored in this location sets the thermostat outpu t to an active - low state. the user has read/write access to the pol bit, and t he power- up default state is 0 (active low). f0, f1 = o.s. fault tolerance bits. the fault tolerance defines the number of consecutive conversions returning a temperature beyond limits is required to set the o.s. output in an active state. this may be necessary to add margin in noisy environments. table 5 defines the four settings. the ds1775 power s up with f0 = f1 = 0, such that a single occurrence trigger s a fault. table 5 . fa ult tolerance configuration f1 f0 consecutive conversions beyond limits to generate fault 0 0 1 0 1 2 1 0 4 1 1 6 downloaded from: http:///
ds1775 7 of 14 r0, r1 = thermometer resolution bits. table 6 defines the resolution of the digital thermometer, based on the settings of these two bit s. there is a direct trade - off between resolution and conversion time, as shown in the ac electrical characteristics . the default state is r0 = 0 and r1 = 0 (9 -bit conversions). table 6 . thermometer resolution configuration r1 r0 thermometer resolution ( bits) max conversion time (seconds) 0 0 9 0.1875 0 1 10 0.375 1 0 11 0.75 1 1 12 1.5 thermostat setpoints programming the thermostat registers (t os and t hyst ) can be programmed or read via the 2 - wire interface. t os is accessed by setting the ds1775 d ata pointer to the 03h location, and to the 02h location for t hyst . the format of the t os and t hyst registers is identical to that of the thermometer register; that is, 1 2 - bit 2s complement representation of the temperature in c. the user can program the number of bits (9, 10, 11, or 12) for each t os and t hyst that corresponds to the thermometer resolution mode chosen. for example, if the 9 - bit mode is chosen the three least significant bits of t os and t hyst are ignored by the thermostat comparator. tabl e 7 shows the format for both t os and t hyst . the power - up default for t os is +80 c and for t hyst is +75 c. table 7 . thermostat setpoint (t os /t hyst ) format s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb msb (unit = c) lsb 2 -1 2 -2 2 -3 2 -4 0 0 0 0 lsb temperature ( c) digital output (binary) digital output (hex) +80 0101 0000 0000 0000 5000h +75 0100 1011 0000 0000 4b00h +10.125 0000 1010 0010 0000 0a20h +0.5 0000 0000 1000 0000 0080h 0 0000 0000 0000 0000 0000h -0.5 1111 1111 1000 0000 ff80h -10.125 1111 0101 1110 0000 f5e0h -25.0625 1110 0110 1111 0000 e6f0h -55 1100 1001 0000 0000 c900h if the user does not wish to take advantage of the thermostat capabilities of the ds1775, t he 24 bits can be used for general storage of system data that need not be maint ained following a power loss. downloaded from: http:///
ds1775 8 of 14 2- wire serial data bus the ds1775 supports a bidirectional 2 - wire bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. the device th at controls the message is called a master. the devices that are controlled by th e master are slaves. the bus must be controlled by a master device which generates the serial clock (s cl), controls the bus access, and generates the start and stop condit ions. the ds1775 operates as a slave on the 2- wire bus. connections to the bus are made via the open-drain i/o lines sda and scl. the following bus protocol has been defined (s ee figure 3 ): ? data transfer may be initiated only when the bus is not busy. ? du ring data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high are interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: bot h data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, whi le the clock is high, defines a start condition. stop data transfer: a change in the state of the data line, from low to high, while t he clock line is high, defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock sig nal. the data on the line must be chan ged during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and termi nated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited, and is determined by the master device. the information is transferred b yte - wise and each receiver acknowledges with a ninth bit. within the bus specifications a standard mode (100khz clock rate) and a fast mode (400khz clock rate) are defin ed. the ds1775 works in both modes. acknowledge: each receiving device, when addressed, is obliged to generate an ack nowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the las t byte that has been clocked out of the slave. in this case, the slave must leave the data line high t o enable the master to generate the stop condition. downloaded from: http:///
ds1775 9 of 14 figure 3. data transfer o n 2 - wire serial bus figure 3 details how data transfer is accomplished on the 2- wire bus. depending upon the state of the r/ w bit, two types of data transfer are possible: 1) data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes . the slave returns an acknowledge bit after each received byte. 2) data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bi t. next follows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at th e end of the last received byte, a not acknowledge is returned. the master device generates all the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. s ince a repeated st art condition is also the beginning of the next serial transfer, the bus is not released. the ds1775 can operate in the following two modes: 1) slave receiver mode: serial data and clock are received through sda and scl. after each byte is received, an ackno wledge bit is transmitted. start and stop conditions are recog nized as the beginning and end of a serial transfer. address recognition is pe rformed by hardware after reception of the slave address and direction bit. 2) slave transmitter mode: the first byte is received and handled as in the slave receiver mod e. however, in this mode, the direction bit indicate s that the transfer direction is reversed. serial data is transmitted on sda by the ds1775 while the serial clock is input on s cl. start and stop conditions are recognized as the beginning and end of a serial transfer. slave address a control byte is the first byte received following the start c ondition from the master device. the control byte consists of a 4- bit control code; for the ds1775, this is set as 1001 binary for read and write operations. the next three bits of the control byte are the device s elect bits (a2, a1, a0). these bits are set to 000 (a2 = 0, a1 = 0, a0 = 0) for the ds1775r and vary according t o the device s p art number as specified in the ordering information table . they are used by the master device to select which of eight devices are to be accessed. the set bits are in effect the three leas t significant bits of the slave address. the last bit of the control byte (r/ w ) defines the operation to be performed. when set to a 1 a read operation is selected; when set to a 0 a write operation is selected. following the start condition, the ds1775 monitors the sda bus checking the device type identifier being transmitted. upon receiving the 1001 code and appropriate device select bits of 000, the ds1775 outputs an acknowl edge signal on the sda line. see figure 4. downloaded from: http:///
ds1775 10 of 14 figure 4. 2 - wire serial communication with ds1775 downloaded from: http:///
ds1775 11 of 14 absolute maximum ratings (voltages relative to ground.) voltage range on v dd -0.3v to +7.0v voltage range on any other p in -0.3v to +7.0v operating temperature range -55 c to +125 c storage temperature range -55 c to +125 c lead temperature (soldering, 10s) +300c soldering temperature (reflow) +260c this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute m aximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics ( 2.7v ? v dd ?? 5.5v, t a = - 55 c to +125 c , unless otherwise noted. ) parameter symbol condition min typ max units notes supply voltage v dd 2.7 5.5 v 1 input logic - high v ih 0.7v dd v dd +0.5 v 1 input logic - low v il -0.5 0.3v dd v 1 sda output logic - low vol tage v ol1 3ma sink current 0 0.4 v 1 v ol2 6ma sink current 0 0.6 o.s. saturation voltage v ol 4ma sink current 0.8 v 1, 9 input current ea ch i/o p in 0.4 < v i/o < 0.9v dd -10 +10 a 2 i/o capacitance c i/o 10 pf standby current i dd1 1 a 3, 4 active current i dd active t emp conversions 1000 a 3, 4 communication only 100 digital thermometer thermometer error t err - 10 c to +85 c 2.0 c 9, 10 - 55 c to +125 c 3.0 resolution 9 12 bits conversion time t convt 9- bit conversion 125 187.5 ms 10- bit conversion 250 375 11- bit conversion 500 750 12- bit conversion 1000 1500 downloaded from: http:///
ds1775 12 of 14 ac electrical characteristics: 2- wire interface (v dd = 2.7v to 5.5v, t a = - 55 c to +125 c , unless otherwise noted. ) (figure 5) para meter symbol condition s min typ max units notes scl clock frequency f scl fast mode 400 khz standard mode 100 bus free time between a stop and start condition t buf fast mode 1.3 s standard mode 4.7 hold time (repeated) start condition t hd:sta fast mode 0.6 s 5 standard mode 4.0 low period of scl t low fast mode 1.3 s standard mode 4.7 high period of scl t high fast mode 0.6 s standard mode 4.0 setup time for a repeated start t su:sta fast mode 0.6 s standard mode 4.7 data hold time t hd:dat fast mode 0 0.9 s 6 standard mode 0 0.9 data setup time t su:dat fast mode 100 ns 7 standard mode 250 rise time of both sda and scl signals t r fast mode 20 + 0.1c b 300 ns 8 standard mode 20 + 0.1c b 1000 fall time of both sda and scl signals t f fast mode 20 + 0.1c b 300 ns 8 standard mode 20 + 0.1c b 300 setup time for stop t su:sto fast mode 0.6 s standard mode 4.0 capacitive load for each bus line c b 400 pf 8 input capacitance c i 5 pf notes: 1. all voltages are referenced to ground. 2. i/o pins of fast mode devices must not obstruct the sda and scl lines if v dd is switched off. 3. i dd specified with o.s. pin open. 4. i dd specified with v dd at 5.0v and v sda , v scl = 5. 0v, 0 c to +70 c. 5. after this period, the first clock pulse is generated. 6. the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. 7. a fast mode device can be used in a standard mode system, but the r equi rement t su:dat 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max +t su:dat = 1000 + 250 = 1250 ns before the scl line is released. 8. c b = t otal capacitance of one bus line in pf. 9. internal heating caused by o.s. loading cause s the ds1775 to read approximately 0.5oc higher if o.s. is sinking the max rated current. 10. contact th e factory for operation requiring temperature readings greater th an +120c. downloaded from: http:///
ds1775 13 of 14 figure 5. timing diagram ordering information part address top mark temp range pin - package ds1775r+u 000 7750 -55 c to +125 c 5 sot23 ds1775r+t&r ds1775r1+u 001 7751 -55 c to +125 c 5 sot23 ds1775r1+t&r ds1775r2+u 010 7752 -55 c to +125 c 5 sot23 ds1775r2+t&r ds1775r3+u 011 7753 -55 c to +125 c 5 sot23 ds1775r3+t&r ds1775r4+u 100 7754 -55 c to +125 c 5 sot23 ds1775r4+t&r ds1775r5+u 101 7755 -55 c to +125 c 5 sot23 ds1775r5+t&r ds1775r6+u 110 7756 -55 c to +125 c 5 sot23 ds1775r6+t&r ds1775r7+u 111 7757 -55 c to +125 c 5 sot23 ds1775r7+t&r + denotes a lead(pb) - free/rohs - compliant package. u = c ut t ape . t&r = tape and reel. packag e information for the latest package outline information and land patterns ( footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status o nly. package drawings may show a different suffix character, but the drawing pertains to the package regardless of r ohs status. package type package code outline no. land pattern no. 5 sot 23 u5+1 21-0057 90-0174 downloaded from: http:///
ds1775 14 of 14 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product . no circuit paten t licenses are implied. maxim integrated reserves the right to change the ci rcuitry and specifications without notice at any time. the parame tric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted i n this data sheet are provided for guidance. maxim integrated 160 rio robles , san jose, ca 95134 usa 1 - 408 - 601 - 1000 ? 201 3 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trade marks of maxim integrated products, inc. revision history revision date description pages changed 5/13 updated the absolute maximum ratings , ordering information , pa ckage information sections 12, 13 downloaded from: http:///

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